Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
A flash memory is a type of memory that can be erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The data in a cell is determined by the presence or absence of the charge in the floating gate. The charge can be removed from the floating gate by a block erase operation.
Flash memory devices typically use fuse elements for storing control, trimming, and/or operational status data. For example, memory lock bits might be stored in a mini-array of fuse elements to indicate when a block of flash memory is write protected.
A row of fuse elements in a mini-array share the same word line. Therefore, when a programming voltage is applied to a particular word line, all of the cells on that word line experience the same programming voltages. This can cause word line stress to the inhibited cells on the word line. The inhibited cells are experiencing a program disturb condition.
Additionally, if a programmed cell does not have a high enough programmed voltage, the cell will leak causing a stand-by current. Therefore, programmed cells must be programmed to raise their threshold voltage high enough to reduce the leakage. This strong of programming can be achieved by a high program gate voltage or by increasing the program time. Either method increases the program stress experienced by the other cells on the word line. In fact, the erased cells on the word line may even be slightly programmed due to the stress.
FIG. 1 illustrates a typical prior art fuse repair method to fix fuses that have experienced a word line stress condition. The method first erases the fuse memory cells 101 and then determines which cells in the main memory array have failed 103. The addresses of the failed bits are loaded into the fuse circuitry along with the I/O information 105. The fuse memory cells are then programmed with the loaded information 107.
Since the fuse cells are programmed during the manufacturing process, the optimum programming condition needs to be found during this time. This typically requires the test engineer to monitor each NAND string cell current after programming. The programming and monitoring is repeated until the current is low enough to indicate a programmed state.
One problem with this approach, however, is large amount of time required to complete the programming/monitoring step. When this time is multiplied over the large quantities of memory IC's that a manufacturer produces, it can greatly reduce the manufacturer's output, thereby increasing the cost of each part.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a more efficient, less stressful fuse memory cell repair method.